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  • Simon,

    Quote"
    (Use photoshop and draw a line from the start to the end of the sawtooth ramp and you can see how it is decreasing in slope.)

    If the TX current was a perfect linear ramp, even the fast target should be still increasing and approaching a constant level, and naturally way ahead of the slow target.

    Pretty sure I got that right..."

    Attached is a sim, as well as a .jpg where the TX coil TC is 20ms. We can assume that during the first 100us the TX ramp is very close to linear.

    Look at the 15us target eddy currents. The eddy current maximum during TX ON, seems to be governed by the TC of the target. After 5 TC, we can see very little increase.

    Tinkerer
    Attached Files

    Comment


    • Originally posted by Tinkerer View Post
      Simon,

      Quote"
      (Use photoshop and draw a line from the start to the end of the sawtooth ramp and you can see how it is decreasing in slope.)

      If the TX current was a perfect linear ramp, even the fast target should be still increasing and approaching a constant level, and naturally way ahead of the slow target.

      Pretty sure I got that right..."

      Attached is a sim, as well as a .jpg where the TX coil TC is 20ms. We can assume that during the first 100us the TX ramp is very close to linear.

      Look at the 15us target eddy currents. The eddy current maximum during TX ON, seems to be governed by the TC of the target. After 5 TC, we can see very little increase.

      Tinkerer
      Well you're totally right about that. The slower target just won't reach the high peak current because it can't move fast enough in response to that "flyback" spike.

      Like hitting different size bricks on a frozen pond with a hammer. The big ones don't respond fast, although they do get about the same momentum. Probably there is an optimum size brick for maximum energy transfer.

      However, we were previously comparing the different ramp-up currents (sawtooth, flattop) and their effects on a target of a given type. In that case, it seemed to me that the target peak-to-peak response did not depend strongly on the ramp-up profile so long as the same current was achieved in the TX coil just before "flyback".

      The point about the slight non-linearity of the sawtooth was to explain why the fast target "charging" current started to actually decline prior to "flyback", as opposed to just approaching a steady state DC value.

      But back to your observation about the TC of targets affecting their response. What's interesting to me is that although the slow targets do not achieve as high a peak current, their current persists longer. If in fact our RX coil has a slow response, its received signal can benefit from the longer response of the slow target, and therefore possibly achieve a higher target signal than you might expect compared to the fast target.

      In other words, if the RX coil response is much slower than both the fast and slow targets, you may not see much difference in the received signal as you would expect, even though the target eddy currents themselves look very different.

      But if we worked the equations (or tinker enough), we might find that we can tune our flyback pulse duration and RX coil time constant to optimize detection of a certain size (TC) target. I guess that is one of the questions we have been pushing toward. When we get a full simulation of all the relevant MD circuitry as you suggested, probably will see some interesting answers!

      -SB

      Comment


      • Originally posted by Tinkerer View Post
        Try the attached sim, the effect is still there.

        It definitely has to do with the model and I think the model is correct. I also think that Midas has shown the cause, but how do we fix it?

        We want a Spice model that is as similar as possible to a real detector. As Carl's post shows, this glitch really exists. A 100 Ohm resistor fixes this glitch, but brings other problem with the switching of the Mosfet.

        Can anybody come up with a good Mosfet drive simulation model?

        These sims show a target response on the target level. Now we want to get these responses to the pre-amp. I have used a large coupling factor from TX to target, so we can easy see the response. However, the coupling is in fact very much lower.

        Then we want to represent an RX coil and a Bucking coil for an IB coil assembly.
        Once e have all the individual parts modeled, we can then see how differences in the assembly or sizes or inductance change the shape or behavior of the target response and RX signal.

        Along the way, this can answer many questions, as seen with the TX current glitch seen above.

        Tinkerer
        Just a note about LTSpice. I played with some simulations where I used very tiny coil coupling constants. I found that LTSpice had trouble doing accurate simulations -- it gave answers, but they had big errors that mislead me. I tried to tweak the LTSpice processing parameters, but it was hard to know if the simulations were accurate in the end.

        Just something to watch out for. Maybe it is still better to use hefty coupling constants and get useful qualitative answers.

        -SB

        Comment


        • Hi all,

          the origin of the switch-on glitch problem is as follows:
          The parasitic coil capacitance is beeing charged from the turned on mosfet by the ideal bypass capacitor (1000 µF). As both caps are ideal, the current spike is high.

          -> Use real (elco) capacitors (having defined Rs, Rp, Ls...)
          -> Don't use any diodes and mosfets from the LTSpice library. Use the manufacturer specific spice models.
          -> Fill the inductor model completely (Rs, Rp, Cp...)

          For more accurate results, fill the "maximum timestep" parameter in the transient analysis card (1µ or 100n or even lower).

          And optionally put the command card
          .options Gmin=1e-12 (if it doesn't convergate, reduce by x10 -> 1e-11, reduce until it convergates)
          .options reltol=0.001 (the higher, the course)

          Cheers,

          Aziz


          PS:
          BTW, don't look at the target currents. If you can, you should look at it's first derivation of it via d(I(Lx)), which is direct proportional to the received voltage in a receive coil.

          Comment


          • Originally posted by Carl-NC View Post
            Unfortunately there are advantages to either. E.g., what's better, a large coil or a small coil?
            I bet, no one in White's knows the correct answer to my question.

            Aziz

            Comment


            • Ok,

              the lumped and simplified LTSpice inductor model seems to work bad. Use the discrete solution (L, Rs, Rp, Cp model). If you add all the currents I(L)+I(Cp)+I(Rp), then you get exactly the same current of the lumped model.

              Aziz

              Problem solved. Next problem.

              Comment


              • Originally posted by simonbaker View Post
                Hi Qiaozhi:

                I think reason is: you are comparing the currents in the coils, rather than the currents into the coil equivalent networks.

                If you put a .000001 ohm resistor in the circuit branch to the discreet model, and compare the current through that to the current through the first coil (lumped model), the currents match up better.

                -SB
                I ran your modified simulation (with the 0.00000001 ohm series resistor) and the results look exactly the same as before. However, I agree that the problem does have something to do with measuring the current through an equivalent network versus a single inductor. To test this theory, I took Tinkerer's simulation file (TEM.asc) and modified it to include a second identical circuit, but with a discrete network TEM2.asc). Again, in this case, the current in L1 (with glitches) does not match the current in L8 (without glitches). With your idea in mind, I then measured the current in the 500pF cap (C9), which is across L8. Then you can easily see the cause of the glitching.

                This in fact compares well with reality, except that the use of an ideal capacitor in series with the coil makes the glitches seem worse than they are in practice. In some simulations I ran, it was possible for the glitches to reach peaks of current as high as 60A.

                In conclusion, we just need to be careful when using the LTSpice inductor model, and to be aware that any current measurement you add to the plot pane [labelled I(L1), for example] does not represent the current flowing in a single component, but rather the overall equivalent network.
                Attached Files

                Comment


                • Originally posted by Aziz View Post
                  the origin of the switch-on glitch problem is as follows:
                  The parasitic coil capacitance is beeing charged from the turned on mosfet by the ideal bypass capacitor (1000 µF). As both caps are ideal, the current spike is high.
                  Removing the 1000uF cap makes no difference to the amplitude of the glitches, but it does affect the maximum current available for charging the coil. In addition, removing both the 1 ohm resistor and the 1000uF cap restores the coil current to the original amplitude, but the glitches remain the same. The problem is definitely due to the ideal parasitic cap across the coil, and has nothing to do with the bypass capacitor.

                  Comment


                  • Originally posted by Qiaozhi View Post
                    I ran your modified simulation (with the 0.00000001 ohm series resistor) and the results look exactly the same as before. However, I agree that the problem does have something to do with measuring the current through an equivalent network versus a single inductor. To test this theory, I took Tinkerer's simulation file (TEM.asc) and modified it to include a second identical circuit, but with a discrete network TEM2.asc). Again, in this case, the current in L1 (with glitches) does not match the current in L8 (without glitches). With your idea in mind, I then measured the current in the 500pF cap (C9), which is across L8. Then you can easily see the cause of the glitching.

                    This in fact compares well with reality, except that the use of an ideal capacitor in series with the coil makes the glitches seem worse than they are in practice. In some simulations I ran, it was possible for the glitches to reach peaks of current as high as 60A.

                    In conclusion, we just need to be careful when using the LTSpice inductor model, and to be aware that any current measurement you add to the plot pane [labelled I(L1), for example] does not represent the current flowing in a single component, but rather the overall equivalent network.
                    Thanks Qiaozhi,

                    C9 across inductance and coil resistance, definitely represents better the parasitic capacitance.

                    There is just one problem left: The glitch on Carl's real circuit.

                    Tinkerer

                    Comment


                    • Originally posted by Qiaozhi View Post
                      I ran your modified simulation (with the 0.00000001 ohm series resistor) and the results look exactly the same as before. However, I agree that the problem does have something to do with measuring the current through an equivalent network versus a single inductor. To test this theory, I took Tinkerer's simulation file (TEM.asc) and modified it to include a second identical circuit, but with a discrete network TEM2.asc). Again, in this case, the current in L1 (with glitches) does not match the current in L8 (without glitches). With your idea in mind, I then measured the current in the 500pF cap (C9), which is across L8. Then you can easily see the cause of the glitching.

                      This in fact compares well with reality, except that the use of an ideal capacitor in series with the coil makes the glitches seem worse than they are in practice. In some simulations I ran, it was possible for the glitches to reach peaks of current as high as 60A.

                      In conclusion, we just need to be careful when using the LTSpice inductor model, and to be aware that any current measurement you add to the plot pane [labelled I(L1), for example] does not represent the current flowing in a single component, but rather the overall equivalent network.
                      Qiaozhi:

                      Did you measure the current through the .0000001 resistor and compare that to the current through the lumped coil?

                      That was the point -- you can't compare coil currents, because LTSpice treats the lumped coil as a 2-port RLC network and displays the port current (I believe), not the current in the ideal inductor. So to compare apples to apples, you have to compare the current into the discrete RLC network (using the .00000001 resistor as a "wire") and compare to the lumped coil current.

                      Maybe I didn't get your point though (it happens ).

                      -SB
                      Attached Files

                      Comment


                      • Originally posted by Aziz View Post
                        Ok,

                        the lumped and simplified LTSpice inductor model seems to work bad. Use the discrete solution (L, Rs, Rp, Cp model). If you add all the currents I(L)+I(Cp)+I(Rp), then you get exactly the same current of the lumped model.

                        Aziz

                        Problem solved. Next problem.
                        Yes, that's what I'm saying too. I don't think that is a problem with LTSpice -- it simply treats the lumped inductor as a two-port network and measures the total current into (and out of) the ports -- it doesn't measure what goes on inside when you ask for the inductor current. That's what I would expect.

                        -SB

                        Comment


                        • Originally posted by simonbaker View Post
                          Qiaozhi:

                          Did you measure the current through the .0000001 resistor and compare that to the current through the lumped coil?

                          That was the point -- you can't compare coil currents, because LTSpice treats the lumped coil as a 2-port RLC network and displays the port current (I believe), not the current in the ideal inductor. So to compare apples to apples, you have to compare the current into the discrete RLC network (using the .00000001 resistor as a "wire") and compare to the lumped coil current.

                          Maybe I didn't get your point though (it happens ).

                          -SB
                          OK - I understand what you were doing now. Yes, now I can see they're the same.
                          By the way, if you rotate the resistor by 180 degrees and replace it, the current plots can be overlaid with the correct polarity. Actually, the correct way to do this in SPICE is to use a zero-volt voltage source. Make sure you place it with the positive terminal on the left.
                          It certainly looks like we've found the real source of the problem. Good job!

                          Comment


                          • Originally posted by Tinkerer View Post
                            Thanks Qiaozhi,

                            There is just one problem left: The glitch on Carl's real circuit.

                            Tinkerer
                            Why is that surprising?

                            -SB

                            Comment


                            • Originally posted by Tinkerer View Post
                              Thanks Qiaozhi,

                              C9 across inductance and coil resistance, definitely represents better the parasitic capacitance.

                              There is just one problem left: The glitch on Carl's real circuit.

                              Tinkerer
                              I don't think the simulation disagrees with the real circuit. In reality there will be a parasitic capacitance across the coil, but it also has an equivalent series resistance. That resistance is not modelled in the inductor network, and this makes the glitches look worse than they really are in practice.

                              The large glitch in Carl's plot is most likely caused by Miller effect, as pointed out by Midas several posts back. This seems to be a different issue.

                              Comment


                              • I cascoded the NMOS and the glitch remained, so I'm doubtful that it is CDG feedthrough. Interesting.

                                Comment

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